 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| S3C7335/P7335 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C7335 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as LCD direct drive capability, 4-channel A/D converter, 8-bit timer/counter, watch timer and PLL frequency synthesizer, it offers you an excellent design solution for a wide variety of applications that require LCD functions and audio applications. Up to 56 pins of the 80-pin QFP package, it can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C7335's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C7335 microcontroller is also available in OTP (One Time Programmable) version, S3P7335. The S3P7335 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7335 is comparable to S3C7335, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C7335/P7335 FEATURES Memory * * A/D Converter * 512-nibble RAM 16K-byte ROM 4-channels with 8-bit resolution Bit Sequential Carrier Buffer I/O Pins * * * * Input only: 4 pins Output only: 28 pins I/O: 24 pins * * Support 16-bit serial data transfer in arbitrary format Level = 300 mVp-p (min) AMVCO range = 0.5 MHz to 30 MHz FMVCO range = 30 MHz to 150 MHz PLL Frequency Synthesizer LCD Controller/Driver * * * * Maximum 14-digit LCD direct drive capability 28 segment x 4 common signals Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 16-Bit Intermediate Frequency (IF) Counter * * * Level = 300 mVp-p (min) AMIF range = 100 kHz to 1 MHz FMIF range = 5 MHz to 15 MHz 8-Bit Basic Timer * * Programmable interval timer functions Watch-dog timer function 8-Bit Timer/Counter * * * * * Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider Serial I/O interface clock generator Watch Timer * * * Time interval generation : 0.5 s, 3.9 ms at 32.768 kHz Frequency outputs to BUZ pin Clock source generation for LCD 8-Bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode Data direction selectable (LSB-first or MSB-first) Internal or external clock source 1-2 S3C7335/P7335 PRODUCT OVERVIEW FEATURES (Continued) Interrupts * * * Instruction Execution Times * * Four internal vectored interrupts Four external vectored interrupts Two quasi-interrupts 0.9, 1.8, 14.2 s at 4.5 MHz 122 s at 32.768 kHz (subsystem) Operating Temperature Memory-Mapped I/O Structure * * - 40 C to 85 C Data memory bank 15 Operating Voltage Range * * Three Power-Down Modes * * * * 1.8 V to 5.5 V at 3MHz PLL/IFC operation: 2.5V to 3.5V or 4.0V to 5.5V Idle: Only CPU clock stops Stop1: Main system or subsystem clock stops Stop2: Main system and subsystem clock stop CE low: PLL and IFC stop Package Type * 80-pin QFP Oscillation Sources * * * * * Crystal or ceramic oscillator for main system clock Crystal for subsystem clock Main system clock frequency: 4.5 MHz (Typ) Subsystem clock frequency: 32.768 kHz (Typ) CPU clock divider circuit (by 4, 8, or 64) 1-3 PRODUCT OVERVIEW S3C7335/P7335 BLOCK DIAGRAM P0.0/BTCO P0.1/TCLO0 P0.2/TCL0 P0.3/BUZ P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 INT0-INT4 I/O Port 0 CE Input Port 1 Interrupt Control Block Clock XTIN RESET XIN XOUT XTOUT Basic Timer Watch Timer Watchdog Timer Timer/ Counter 0 Instruction Register IF Counter PLL Synthesizer LCD Driver/ Controller AMIF FMIF VCOAM VCOFM EO BIAS VLC0-VLC2 COM0-COM3 P13.0-P13.3 /SEG24-SEG27 P12.0-P12.3 /SEG20-SEG23 P11.0-P11.3 /SEG16-SEG19 P10.0-P10.3 /SEG12-SEG15 P9.0-P9.3 /SEG8-SEG11 P8.0-P8.3 /SEG4-SEG7 P7.0-P7.3 /SEG0-SEG3 P6.0-P6.3 KS0-KS3 I/O Port 2 I/O Port 3 Serial I/O Port Internal Interrupts Instruction Decoder Arithmetic and Logic Unit Program Counter Program Status Word P4.0/SCK P4.1/SO P4.2/SI P4.3/CLO P5.0/ADC0 P5.1/ADC1 P5.2/ADC2 P5.3/ADC3 I/O Port 4 Stack Pointer Output Port 11,12,13 I/O Port 5 512 x 4-Bit Data Memory 16K-Byte Program Memory Output Port 7,8,9,10 A/D Converter I/O Port 6 Figure 1-1. S3C7335 Simplified Block Diagram 1-4 S3C7335/P7335 PRODUCT OVERVIEW PIN ASSIGNMENTS VDD1 E0 CE P3.0 P3.1 P3.2 P3.3 P0.0/BTCO P0.1/TCLO0 P0.2/TCL0 P0.3/BUZ P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P4.0/SCK 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P4.1/SO P4.2/SI P4.3/CLO P5.0/ADC0 P5.1/ADC1 P5.2/ADC2 P5.3/ADC3 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 VDD0 VSS0 XOUT XIN TEST XTIN XTOUT RESET BIAS VLC0 VLC1 VLC2 COM0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3C7335 (80-QFP-Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 FMIF AMIF VSS1 VCOAM VCOFM P2.3 P2.2 P2.1 P2.0 SEG27/P13.3 SEG26/P13.2 SEG25/P13.1 SEG24/P13.0 SEG23/P12.3 SEG22/P12.2 SEG21/P12.1 SEG20/P12.0 SEG19/P11.3 SEG18/P11.2 SEG17/P11.1 SEG16/P11.0 SEG15/P10.3 SEG14/P10.2 SEG13/P10.1 Figure 1-2. S3C7335 80-QFP Pin Assignment 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEG12/P10.0 SEG11/P9.3 SEG10/P9.2 SEG9/P9.1 SEG8/P9.0 SEG7/P8.3 SEG6/P8.2 SEG5/P8.1 SEG4/P8.0 SEG3/P7.3 SEG2/P7.2 SEG1/P7.1 SEG0/P7.0 COM3 COM2 COM1 1-5 PRODUCT OVERVIEW S3C7335/P7335 PIN DESCRIPTIONS Table 1-1. S3C7335 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0-P2.3 P3.0-P3.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read, write, and test are possible. Pull-up resistors can be configured by software. 4-bit input port. 1-bit or 4-bit read and test are possible. Pull-up resistors can be configured by software. 4-bit I/O ports. 1-bit, 4-bit or 8-bit read, write and test are possible. Pull-up resistors can be configured by software. Ports 2 and 3 can be paired to support 8-bit data transfer. 4-bit I/O ports. 1-bit, 4-bit or 8-bit read, write and test are possible. Pull-up resistors can be configured by software. Ports 4 and 5 can be paired to support 8-bit data transfer. Number 72 73 74 75 76 77 78 79 56-59 68-71 Share Pin BTCO TCLO0 TCL0 BUZ INT0 INT1 INT2 INT4 - Reset Value Input Circuit Type D-2 D-2 D-4 D-2 A-4 I Input I/O Input D-2 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 P6.1 P6.2 P6.3 P7.0 P7.1 P7.2 P7.3 P8.0 P8.1 P8.2 P8.3 P9.0 P9.1 P9.2 P9.3 P10.0 P10.1 P10.2 P10.3 I/O 80 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 SCK SO SI CLO ADC0 ADC1 ADC2 ADC3 KS0 KS1 KS2 KS3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 Input D-4 D-2 D-4 D-2 F-10 I/O Input I/O 4-bit I/O port. 1-bit, 4-bit or 8-bit read, write and test are possible. Pull-up resistors can be configured by software. 1-bit or 4-bit output port. Alternatively used for LCD segment output. Input D-7 O Output H-28 O 1-bit or 4-bit output port. Alternatively used for LCD segment output. Output H-28 O 1-bit or 4-bit output port. Alternatively used for LCD segment output. SEG8 Output SEG9 SEG10 SEG11 SEG12 Output SEG13 SEG14 SEG15 H-28 O 1-bit or 4-bit output port. Alternatively used for LCD segment output. H-28 1-6 S3C7335/P7335 PRODUCT OVERVIEW Table 1-1. S3C7335 Pin Descriptions (Continued) Pin Name P11.0 P11.1 P11.2 P11.3 P12.0 P12.1 P12.2 P12.3 P13.0 P13.1 P13.2 P13.3 COM0COM3 BIAS VLC0 VLC1 VLC2 VDD0 VSS0 RESET XOUT XIN XTOUT XTIN TEST CE I I - - - I - Main power supply Main Ground System reset pin Crystal, or ceramic oscillator pin for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) Crystal oscillator pin for subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) Test signal input (must be connected to VSS for normal operation) Input pin for checking device power. Normal operation is high level and PLL/IFC operation is stopped at low level. External VCOFM/AM signal inputs. PLL's phase error output FM/AM intermediate frequency signal inputs. PLL/IFC power supply PLL/IFC ground 12 13 19 14 15 18 17 16 67 - - - - - - Input - - - B - Pin Type O Description 1-bit or 4-bit output port. Alternatively used for LCD segment output. Number 44 45 46 47 48 49 50 51 52 53 54 55 24-27 20 21 22 23 Share Pin Reset Value Circuit Type H-28 SEG16 Output SEG17 SEG18 SEG19 SEG20 Output SEG21 SEG22 SEG23 SEG24 Output SEG25 SEG26 SEG27 - - - Output Input Input O 1-bit or 4-bit output port. Alternatively used for LCD segment output. H-28 O 1-bit or 4-bit output port. Alternatively used for LCD segment output. H-28 O I I Common signal output for LCD display LCD power control LCD power supply. Voltage dividing resistors are assignable by software H - - - - - - - - Input - B-5 VCOFM VCOAM EO FMIF AMIF VDD1 VSS1 I O I - - 60 61 66 64 63 65 62 - - Input - - Input Output - - - B-4 A-2 B-4 - - 1-7 PRODUCT OVERVIEW S3C7335/P7335 Table 1-1. S3C7335 Pin Descriptions (Concluded) Pin Name BTCO TCLO0 TCL0 BUZ Pin Type I/O I/O I/O I/O Description Basic timer overflow output signal Timer/counter 0 clock output signal External clock input for timer/counter 0 2,4,8 or 16 kHz frequency output for buzzer sound for 4.19 MHz main system clock or 32.768 kHz subsystem clock External interrupt. The triggering edges (rising/falling) are selectable. Only INT0 is synchronized with system clock. Quasi-interrupt with detection of rising edge signal. External interrupt input with detection of rising or falling edges. SIO interface clock signal SIO interface data input signal SIO interface data output signal CPU clock output Quasi-interrupt input with falling edge detection ADC input ports. LCD segment signal output. LCD segment signal output. Number 72 73 74 75 Share Pin P0.0 P0.1 P0.2 P0.3 Reset Value Input Input Input Input Circuit Type D-2 D-2 D-4 D-2 INT0 INT1 INT2 INT4 SCK SI SO CLO KS0-KS3 ADC0ADC3 SEG0SEG3 SEG4SEG27 I 76 77 78 79 80 1 2 3 8-11 4-7 28-31 32-55 P1.0 P1.1 P1.2 P1.3 P4.0 P4.2 P4.1 P4.3 P6.0P6.3 P5.0P5.3 P7.0P7.3 P8-P13 Input A-4 I I I/O I/O I/O I/O I/O I/O O O Input D-4 Input Input Output Output D-7 F-10 H-28 H-28 1-8 S3C7335/P7335 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-Up Resistor In P-Channel In N-Channel Schmitt Trigger Figure 1-3. Pin Circuit Type A Figure 1-6. Pin Circuit Type B (RESET RESET) VDD In Up P-Channel Out Down N-Channel N-CH Type A Feedback Enable Pull-Down Enable Figure 1-4. Pin Circuit Type A-2(EO) Figure 1-7. Pin Circuit Type B-4 VDD In Pull-Up Enable In Figure 1-5. Pin Circuit Type A-4 (P1) Figure 1-8. Pin Circuit Type B-5(CE) 1-9 PRODUCT OVERVIEW S3C7335/P7335 VDD VDD Pull-up Enable Data P-Channel Out Output Disable N-Channel Data Output Disable Circuit Type C I/O P-Channel Schmitt Trigger Figure 1-9. Pin Circuit Type C Figure 1-11. Pin Circuit Type D-4 VDD VDD Pull-up Enable Data Output Disable P-Channel Pull-up Enable Data P-Channel Circuit Type C I/O Output Disable Circuit Type C I/O Port Enable Schmitt Trigger Figure 1-10. Pin Circuit Type D-2 Figure 1-12. Pin Circuit Type D-7 (P6) 1-10 S3C7335/P7335 PRODUCT OVERVIEW VDD VLC0 Pull-up Enable Data Output Disable Circuit Type C VLC1 I/O SEG ADCEN Out Output Disable ADC Select Data VLC2 TO ADC Figure1-13. Pin Circuit Type F-10 (P5) Figure 1-15. Pin Circuit Type H-4 VLC0 PNE VLC1 P-CH Data LCD COM Out Output DIsable N-CH Output VDD VLC2 SEG Circuit Type H-4 Figure 1-14. Pin Circuit Type H (COM0-COM3) Figure 1-16. Pin Circuit Type H-28 (P7-P13) 1-11 S3C7335/P7335 ELECTRICAL DATA 17 OVERVIEW -- I/O capacitance ELECTRICAL DATA In this section, information on S3C7335 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- System clock oscillator characteristics -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- Input timing for RESET -- Input timing for external interrupts and Quasi-Interrupts Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request 17-1 ELECTRICAL DATA S3C7335/P7335 Table 17-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VIN VO IOH IOL Conditions - Applies to all I/O ports - One I/O port active All I/O ports active Output current low One I/O port active Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 -30 + 30 (peak value) + 15 (note) Total value for output ports Operating temperature Storage temperature TA TSTG Duty . Units V mA + 100 (peak value) + 60 * - 40 to + 85 - 65 to + 150 C NOTE: The values for output current low ( IOL ) are calculated as Peak Value x 17-2 S3C7335/P7335 ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 VOH2 Conditions All input pins except those specified below P0.2, P1, P4.0, P4.2, P5, P6, CE and RESET XIN, XOUT, XTIN, and XTOUT All input pins except those specified below P0.2, P1, P4.0, P4.2, P5, P6, CE and RESET XIN, XOUT, XTIN, and XTOUT VDD = 4.5 V to 5.5 V, EO; IOH = - 1 mA VDD = 4.5 V to 5.5 V; Other output ports; IOH = - 1 mA VDD = 4.5 V to 5.5 V, EO; IOL = 1 mA, VDD = 4.5 V to 5.5 V Other output ports; IOL = 10 mA VIN = VDD All input pins VIN = 0 V All input pins VOUT = VDD All output pins VDD-2.0 VDD-1.0 - Min 0.7 VDD 0.8 VDD VDD-0.1 - - Typ - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 VDD VDD Units V Output low voltage VOL1 VOL2 - - - - - - 2.0 2 3 A Input high leakage current(note) Input low leakage current(note) Output high leakage current(note) ILIH ILIL - - -3 ILOH - - 3 NOTE: Except for XIN , XOUT, XTIN and XTOUT. 17-3 ELECTRICAL DATA S3C7335/P7335 Table 17-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter VLC0 output voltage VLC1 output voltage VLC2 output voltage COM output voltage deviation SEG output voltage deviation LCD output voltage deviation Oscillator feed back resistors Symbol VLC0 VLC1 VLC2 VDC TA = 25 C TA = 25 C TA = 25 C VDD = 5V, (VLC0 - COMi I = 0 - 3 ) IO = 15 A (I = 0 - 3) VDD = 5V, (VLC0 - COMi I = 0 - 3 ) IO = 15 A (I = 0 - 3) TA = 25 C VDD = 5.0 V, TA = 25 C XIN = VDD, XOUT = 0 V VDD = 5.0 V, TA = 25 C XTIN = VDD, XTOUT = 0 V VDD = 5.0 V, VIN = VDD; VCOFM, VCOAM, AMIF, and FMIF VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 4, 5, and 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V RESET Conditions Min 0.6 VDD- 0.2 0.4 VDD- 0.2 0.2 VDD- 0.2 - Typ 0.6 VDD 0.4 VDD 0.2 VDD 45 Max 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2 120 Units V mV VDS 45 120 RLCD 70 100 150 K ROSC1 300 600 1500 ROSC2 Pull-down resistor Pll-up Resistor RD RL1 1500 3000 4500 15 25 50 100 30 47 95 220 45 100 200 400 VDD = 3 V 200 450 800 17-4 S3C7335/P7335 ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current(1) Symbol IDD1 (2) Conditions Main operating, PLL operating: PCON = 0011B, SCMOD = 0000B CE = VDD; Crystal oscillator C1 = C2 = 22 pF VDD = 5 V 10% CE Low, PCON = 0011B, SCMOD = 0000B CE = 0 V Crystal oscillator C1 = C2 = 22 pF VDD = 5 V 10% VDD = 3 V 10% 4.5 MHz Min - Typ 5.5 Max 27 Units mA IDD2 (2) 6.0 MHz 4.5 MHz - 3.5 2.5 8 5.5 6.0 MHz 4.5 MHz 6.0 MHz 4.5 MHz - 1.6 1.2 1.0 0.9 4 3 2.5 2.0 IDD3 (2) Main idle mode, PCON = 0111B, SCMOD =0000B Crystal oscillator C1 = C2 = 22 pF VDD = 5 V 10% VDD = 3 V 10% 6.0 MHz 4.5MHz - 0.5 0.4 15 1.0 0.8 30 uA IDD4(2) IDD5 (2) IDD6(2) Sub operating mode: PCON = 0011B, SCMOD = 1001B CE = 0 V; VDD = 3 V 10% 32 kHz crystal oscillator Sub idle mode: PCON = 0111B, SCMOD = 1001B CE = 0 V; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode: CPU = fxt/4, SCMOD = 1101B CE = 0 V; VDD = 5 V 10% Stop mode: CPU = fx/4, SCMOD = 0100B VDD = 5 V 10% - 6 15 - 0.5 3 IDD7(2) - NOTES: 1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors. 2. Data includes the power consumption for sub-system clock oscillation. 17-5 ELECTRICAL DATA S3C7335/P7335 Table 17-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT (1) Parameter Oscillation frequency Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ - Max 6 Units MHz C1 C2 Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range. VDD = 2.7 V to 5.5 V - - 4 ms Crystal Oscillator XIN XOUT Oscillation frequency (1) 0.4 - 6 MHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 0.4 - - - 10 30 6 ms External Clock XIN XOUT XIN input frequency (1) - MHz XIN input high and low level width (tXH, tXL) - 83.3 - - ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 17-6 S3C7335/P7335 ELECTRICAL DATA Table 17-4. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration XTIN XTOUT (1) Parameter Oscillation frequency Test Condition - Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 2.7 V to 5.5 V VDD = 1.8 V to 4.5 V - - 32 1.0 - - 2 10 100 s External Clock XTIN XTOUT XTIN input frequency (1) - kHz XTIN input high and low level width (tXTL, tXTH) - 5 - 15 s NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs. 17-7 ELECTRICAL DATA S3C7335/P7335 Table 17-5. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f CLK = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF Table 17-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) Interrupt input high, low width RESET and CE Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Min 0.67 1.3 (2) Typ - Max 64 64 Units s s s tINTH, tINTL tRSL INT0 INT1, INT2, INT4, KS0-KS2 Input - - 10 10 1 - Input Low Width NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting. Table 17-6. A.C. Electrical Characteristics (Continued) (TA = - 10 C to + 70 C, VDD = 3.5 V to 5.5 V) Parameter A/D converting Resolution Absolute accuracy AD conversion time Analog input voltage Analog input impedance Symbol - - tCON VIAN RAN Conditions - - - - VDD = 5 V Min - - 17 VSS 2 Typ 8 - 34/fxx (note) - 1000 Max - 2 - VDD - Units bits LSB s V M NOTE: fxx stands for the system clock (fx or fxt). 17-8 S3C7335/P7335 ELECTRICAL DATA Table 17-6. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.5 V to 3.5 V or VDD = 4.0 V to 5.5 V) Parameter VCOFM, VCOAM, FMIF and AMIF Input Voltage (Peak to Peak) Frequency Symbol VIN Conditions Sine wave input Min 0.3 Typ - Max VDD Units V fVCOAM fVCOFM f AMIF f FMIF VCOAM mode, sine wave input; VIN = 0.3VP-P VCOFM mode, sine wave input; VIN = 0.3VP-P AMIF mode, sine wave input; VIN = 0.3VP-P FMIF mode, sine wave input; VIN = 0.3VP-P 0.5 30 0.1 5 - 30 150 1.0 15 MHz 17-9 ELECTRICAL DATA S3C7335/P7335 Table 17-6. A.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With subsystem clock (fxt) TCL0 input frequency f TI VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 input high, low width SCK cycle time tTIH, tTIL VDD = 2.7. V to 5.5 V VDD = 1.8. V to 5.5 V tKCY VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source SCK high, low width tKH, tKL VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source SI setup time to SCK high SI hold time to SCK high Output delay for SCK to SO tKSO tKSI tSIK External SCK source Internal SCK source External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source 1000 250 1000 tKCY/2-150 100 150 400 400 - - 300 - - - - tKCY/2- 50 1600 3800 400 - - 650 3200 0.48 1.8 800 - - ns - Min 0.67 1.3 114 0 Typ - - 122 - Max 64 64 125 1.5 1 - s MHz Units s NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source. 17-10 S3C7335/P7335 ELECTRICAL DATA CPU Clock 1.5 MHz Main Oscillator Frequency 6 MHz 1.0475 MHz 1 MHz 750 kHz 4.19 MHz 3 MHz 250 kHz 15.6 kHz 1 2 3 4 5 6 7 400 kHz Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) When PLL/IFC operation, operating voltage range is 2.5 V to 3.5 V or 4.0 V to 5.5 V. Figure 17-1. Standard Operating Voltage Range Table 17-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Normal operation VDDDR = 1.8 V Min 1.8 - Typ - 0.1 Max 5.5 1 Unit V A 17-11 ELECTRICAL DATA S3C7335/P7335 TIMING WAVEFORMS Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction RESET tWAIT tSREL Figure 17-2. Stop Mode Release Timing When Initiated by RESET Idle Mode ~ ~ ~ ~ Stop Mode Data Retention Normal Operating Mode VDD VDDDR Execution of STOP Instruction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 17-3. Stop Mode Release Timing When Initiated by an Interrupt Request 17-12 S3C7335/P7335 ELECTRICAL DATA 0.8 VDD Measurement Points 0.2 VDD 0.8 VDD 0.2 VDD Figure 17-4. A.C. Timing Measurement Points (Except for XIN and XTIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 17-5. Clock Timing Measurement at XIN 1/fxt tXTL tXTH XTIN VDD - 0.1 V 0.1 V Figure 17-6. Clock Timing Measurement at XTIN 17-13 ELECTRICAL DATA S3C7335/P7335 tRSL RESET 0.2 VDD Figure 17-7. Input Timing for RESET Signal tINTL tINTH INT0, 1, 2, 4, KS0 to KS2 0.8 VDD 0.2 VDD Figure 17-8. Input Timing for External Interrupts and Quasi-Interrupts 17-14 S3C7335/P7335 MECHANICAL DATA 18 OVERVIEW -- Pad diagram MECHANICAL DATA This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad/pin coordinate data table 23.90 0.30 0-8 20.00 0.20 + 0.10 0.15 - 0.05 17.90 0.30 14.00 0.20 80-QFP-1420C 0.80 0.20 #1 0.80 0.35 + 0.10 0.15 MAX (0.80) 0.10 MAX #80 0.05 MIN 2.65 0.10 3.00 MAX 0.80 0.20 NOTE: Dimensions are in millimeters. Figure 18-1. 80-QFP-1420C Package Dimensions 18-1 S3C7335/P7335 S3P7335 OTP 19 OVERVIEW S3P7335 OTP The S3P7335 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7335 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The S3P7335 is fully compatible with the S3C7335, both in function and in pin configuration. Because of its simple programming requirements, the S3P7335 is ideal for use as an evaluation chip for the S3C7335. 19-1 S3P7335 OTP S3C7335/P7335 VDD1 E0 CE P3.0 P3.1 P3.2 P3.3 P0.0/BTCO P0.1/TCLO0 P0.2/TCL0 P0.3/BUZ P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P4.0/SCK 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.1/SO P4.2/SI P4.3/CLO P5.0/ADC0 P5.1/ADC1 P5.2/ADC2 P5.3/ADC3 P6.0/KS0 P6.1/KS1 SDAT/P6.2/KS2 SCLK/P6.3/KS3 VDD/VDD0 VSS/VSS0 XOUT XIN VPP/TEST XTIN XTOUT RESET /RESET BIAS VLC0 VLC1 VLC2 COM0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3P7335 (80-QFP Top View) FMIF AMIF VSS1 VCOAM VCOFM P2.3 P2.2 P2.1 P2.0 SEG27/P13.3 SEG26/P13.2 SEG25/P13.1 SEG24/P13.0 SEG23/P12.3 SEG22/P12.2 SEG21/P12.1 SEG20/P12.0 SEG19/11.3 SEG18/P11.2 SEG17/P11.1 SEG16/P11.0 SEG15/P10.3 SEG14/P10.2 SEG13/P10.3 Figure 19-1. S3P7335 Pin Assignments (80-QFP) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEG12/P10.0 SEG11/P9.3 SEG10/P9.2 SEG9/P9.1 SEG8/P9.0 SEG7/P8.3 SEG6/P8.2 SEG5/P8.1 SEG4/P8.0 SEG3/P7.3 SEG2/P7.2 SEG1/P7.1 SEG0/P7.0 COM3 COM2 COM1 19-2 S3C7335/P7335 S3P7335 OTP Table 19-1. Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name P6.2 Pin Name SDAT Pin No. 10 I/O I/O During Programming Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input or push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P6.3 TEST SCLK VPP (TEST) 11 16 I/O I RESET VDD / VSS RESET VDD / VSS 19 12/13 I I Table 19-2. Comparison of S3P7335 and S3C7335 Features Characteristic Program Memory Operating Voltage (VDD) S3P7335 16K bytes EPROM 1.8 V to 5.5 V 2.5 V to 3.5 V or 4.0 V to 5.5 V at PLL/IFC operation VDD = 5 V, VPP (TEST) = 12.5 V 80 QFP User Program 1 time 80 QFP Programmed at the factory S3C7335 16K bytes mask ROM 1.8 V to 5.5 V 2.5 V to 3.5 V or 4.0 V to 5.5 V at PLL/IFC operation - OTP Programming Mode Pin Configuration EPROM Programmability OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the Vpp (TEST) pin of the S3P7335, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 19-3. Operating Mode Selection Criteria VDD 5V Vpp(TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM MEM 0 0 0 1 Address(A15-A0) 0000H 0000H 0000H 0E3FH R/W W 1 0 1 0 Mode EPROM read EPROM program EPROM verify EPROM read protection NOTE: "0" means low level; "1" means high level. 19-3 S3P7335 OTP S3C7335/P7335 Table 19-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 VOH2 Conditions All input pins except those specified below P0.2, P1, P4.0, P4.2, P5, P6, CE and RESET XIN, XOUT, XTIN, and XTOUT All input pins except those specified below P0.2, P1, P4.0, P4.2, P5, P6, CE and RESET XIN, XOUT, XTIN, and XTOUT VDD = 4.5 V to 5.5 V, EO; IOH = - 1 mA VDD = 4.5 V to 5.5 V; Other output ports; IOH = - 1 mA VDD = 4.5 V to 5.5 V, EO; IOL = 1 mA, VDD = 4.5 V to 5.5 V Other output ports; IOL = 10 mA VIN = VDD All input pins VIN = 0 V All input pins VOUT = VDD All output pins VOUT = 0 V All output pins VDD-2.0 VDD-1.0 - Min 0.7 VDD 0.8 VDD VDD-0.1 - - Typ - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 VDD VDD Units V Output low voltage VOL1 VOL2 - - - - - - 2.0 2 3 A Input high leakage current(note) Input low leakage current(note) Output high leakage current(note) Output low leakage current (note) NOTE: ILIH ILIL - - -3 ILOH - - 3 ILOL - - -3 Except for XIN, XOUT, XTIN, and XTOUT 19-4 S3C7335/P7335 S3P7335 OTP Table 19-4. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter VLC0 output voltage VLC1 output voltage VLC2 output voltage COM output voltage deviation SEG output voltage deviation LCD output voltage deviation Oscillator feed back resistors Symbol VLC0 VLC1 VLC2 VDC TA = 25 C TA = 25 C TA = 25 C VDD = 5V, (VLC0 - COMi I = 0 - 3 ) IO = 15 A (I = 0 - 3) VDD = 5V, (VLC0 - COMi I = 0 - 3 ) IO = 15 A (I = 0 - 3) TA = 25 C VDD = 5.0 V, TA = 25 C XIN = VDD, XOUT = 0 V VDD = 5.0 V, TA = 25 C XTIN = VDD, XTOUT = 0 V VDD = 5.0 V, VIN = VDD; VCOFM, VCOAM, AMIF, and FMIF VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 4, 5, and 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V RESET Conditions Min 0.6 VDD- 0.2 0.4 VDD- 0.2 0.2 VDD- 0.2 - Typ 0.6 VDD 0.4 VDD 0.2 VDD 45 Max 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2 120 Units V mV VDS 45 120 RLCD 70 100 150 k ROSC1 300 600 1500 ROSC2 Pull-down resistor Pull-up resistor RD RL1 1500 3000 4500 15 25 50 100 30 47 95 220 45 100 200 400 VDD = 3 V 200 450 800 19-5 S3P7335 OTP S3C7335/P7335 Table 19-4. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current(1) Symbol IDD1 (2) Conditions Main operating: PCON = 0011B, SCMOD = 0000B CE = VDD; Crystal oscillator C1 = C2 = 22 pF VDD = 5 V 10% CE Low mate: PCON = 0011B, SCMOD = 0000B CE = 0 V Crystal oscillator C1 = C2 = 22 pF VDD = 5 V 10% VDD = 3 V 10% 4.5 MHz Min - Typ 5.5 Max 27 Units mA IDD2 (2) 6.0 MHz 4.5 MHz - 3.5 2.5 8 5.5 6.0 MHz 4.5 MHz 6.0 MHz 4.5 MHz - 1.6 1.2 1.0 0.9 4 3 2.5 2.0 IDD3 (2) Main idle mode: PCON = 0111B, SCMOD =0000B Crystal oscillator C1 = C2 = 22 pF VDD = 5 V 10% VDD = 3 V 10% 6.0 MHz 4.5MHz - 0.5 0.4 15 1.0 0.8 30 uA IDD4(2) IDD5 (2) IDD6(2) Sub operating mode: PCON = 0011B, SCMOD = 1001B CE = 0 V; VDD = 3 V 10% 32 kHz crystal oscillator Sub idle mode: PCON = 0111B, SCMOD = 1001B CE = 0 V; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode: CPU = fxt/4, SCMOD = 1101B CE = 0 V; VDD = 5 V 10% Stop mode: CPU = fx/4, SCMOD = 0100B VDD = 5 V 10% - 6 15 - 0.5 3 IDD7(2) - NOTES: 1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors. 2. Data includes the power consumption for sub-system clock oscillation. 19-6 S3C7335/P7335 S3P7335 OTP Table 19-5. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT (1) Parameter Oscillation frequency Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ - Max 6 Units MHz C1 C2 Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range. VDD = 2.7 V to 5.5 V - - 4 ms Crystal Oscillator XIN XOUT Oscillation frequency (1) 0.4 - 6 MHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V - - 0.4 - - - 10 30 6 ms External Clock XIN XOUT XIN input frequency (1) - MHz XIN input high and low level width (tXH, tXL) - 83.3 - - ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 19-7 S3P7335 OTP S3C7335/P7335 Table 19-6. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillato r Crystal Oscillator Clock Configuration XTIN XTOUT (1) Parameter Oscillation frequency Test Condition - Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 2.7 V to 5.5 V VDD = 1.8 V to 4.5 V - - 32 1.0 - - 2 10 100 s External Clock XTIN XTOUT XTIN input frequency (1) - kHz XTIN input high and low level width (tXTL, tXTH) - 5 - 15 s NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs. 19-8 S3C7335/P7335 S3P7335 OTP Table 19-7. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f CLK = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF Table 19-8. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) Interrupt input high, low width RESET and CE Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Min 0.67 1.3 (2) Typ - Max 64 64 Units s s s tINTH, tINTL tRSL INT0 INT1, INT2, INT4, KS0-KS2 Input - - 10 10 1 - Input Low Width NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting. Table 19-8. A.C. Electrical Characteristics (continued) (TA = - 10 C to + 70 C, VDD = 3.5 V to 5.5 V) Parameter A/D converting Resolution Absolute accuracy AD conversion time Analog input voltage Analog input impedance Symbol - - tCON VIAN RAN Conditions - - - - VDD = 5 V Min - - 17 VSS 2 Typ 8 - 34/fxx (note) - 1000 Max - 2 - VDD - Units bits LSB s V M NOTE: fxx stands for the system clock (fx or fxt). 19-9 S3P7335 OTP S3C7335/P7335 Table 19-8. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.5 V to 3.5 V or VDD = 4.0 V to 5.5 V) Parameter VCOFM, VCOAM, FMIF and AMIF Input Voltage (Peak to Peak) Frequency Symbol VIN Conditions Sine wave input Min 0.3 Typ - Max VDD Units V fVCOAM fVCOFM f AMIF f FMIF VCOAM mode, sine wave input; VIN = 0.3VP-P VCOFM mode, sine wave input; VIN = 0.3VP-P AMIF mode, sine wave input; VIN = 0.3VP-P FMIF mode, sine wave input; VIN = 0.3VP-P 0.5 30 0.1 5 - 30 150 1.0 15 MHz 19-10 S3C7335/P7335 S3P7335 OTP Table 19-8. A.C. Electrical Characteristics (continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With subsystem clock (fxt) TCL0 input frequency f TI VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 input high, low width SCK cycle time tTIH, tTIL VDD = 2.7. V to 5.5 V VDD = 1.8. V to 5.5 V tKCY VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source SCK high, low width tKH, tKL VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source SI setup time to SCK high SI hold time to SCK high Output delay for SCK to SO tKSO tKSI tSIK External SCK source Internal SCK source External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source 1000 250 1000 tKCY/2-150 100 150 400 400 - - 300 - - - - tKCY/2- 50 1600 3800 400 - - 650 3200 0.48 1.8 800 - - ns - Min 0.67 1.3 114 0 Typ - - 122 - Max 64 64 125 1.5 1 - s MHz Units s NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source. 19-11 S3P7335 OTP S3C7335/P7335 CPU Clock 1.5 MHz Main Oscillator Frequency 6 MHz 1.0475 MHz 1 MHz 750 kHz 4.19 MHz 3 MHz 250 kHz 15.6 kHz 1 2 3 4 5 6 7 400 kHz Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) When PLL/IFC operation, operating voltage range is 2.5 V to 3.5 V or 4.0 V to 5.5 V. Figure 19-2. Standard Operating Voltage Range Table 19-9. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Normal operation VDDDR = 1.8 V Min 1.8 - Typ - 0.1 Max 5.5 1 Unit V A 19-12 S3C7335/P7335 S3P7335 OTP TIMING WAVEFORMS Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction RESET tWAIT tSREL Figure 19-3. Stop Mode Release Timing When Initiated by RESET Idle Mode ~ ~ ~ ~ Stop Mode Data Retention Normal Operating Mode VDD VDDDR Execution of STOP Instruction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 19-4. Stop Mode Release Timing When Initiated by an Interrupt Request 19-13 S3P7335 OTP S3C7335/P7335 0.8 VDD Measurement Points 0.2 VDD 0.8 VDD 0.2 VDD Figure 19-5. A.C. Timing Measurement Points (Except for XIN and XTIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 19-6. Clock Timing Measurement at XIN 1/fxt tXTL tXTH XTIN VDD - 0.1 V 0.1 V Figure 19-7. Clock Timing Measurement at XTIN 19-14 S3C7335/P7335 S3P7335 OTP tRSL RESET 0.2 VDD Figure 19-8. Input Timing for RESET Signal tINTL tINTH INT0, 1, 2, 4, KS0 to KS2 0.8 VDD 0.2 VDD Figure 19-9. Input Timing for External Interrupts and Quasi-Interrupts 19-15 |
Price & Availability of S3P7335
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |